The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop (DLL) of a semiconductor memory device.
A system is implemented with a plurality of semiconductor devices having various functions. Among them, a semiconductor memory device has been used to store data. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells corresponding to addresses inputted together with the data.
As the operating speed of the system is increasing, the data processor requires the semiconductor memory device to input/output data at much higher speed. As semiconductor integrated circuit (IC) technologies are rapidly developed, the operating speed of the data processor increases, but the data input/output speed of the semiconductor memory device does not keep up with the increased operating speed of the data processor.
Many attempts have been made to develop semiconductor memory devices that can increase data input/output speed up to the level required by the data processor. One of these semiconductor memory devices is a synchronous memory device that outputs data at each period of a system clock. Specifically, the synchronous memory device outputs or receives data to or from the data processor in synchronization with the system clock. However, because even the synchronous memory device could not keep up with the operating speed of the data processor, a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device outputs or receives data at each transition of the system clock. That is, the DDR synchronous memory device outputs or receives data in synchronization with falling edges and rising edges of the system clock.
However, the system clock necessarily has a predetermined delay time until it arrives at a data output circuit because it passes through a clock input buffer, a transfer line and the like. Thus, if the data output circuit outputs data in synchronization with the delayed system clock, an external device will receive data that are not synchronized with rising edges (rising transitions) and falling edges (falling transitions) of the system clock.
To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) circuit to lock a delay of a clock signal. The DLL circuit compensates for the delay caused by internal circuits of the semiconductor memory device until the system clock input to the semiconductor memory device is transferred to the data output circuit. The DLL circuit detects the delay time of the system clock, which is caused by the clock input buffer, the clock transfer line and the like. of the semiconductor memory device. Then, the DLL circuit delays the system clock by the detected delay time and outputs the delayed system clock to the data output circuit. That is, the DLL circuit outputs the delay-locked system clock to the data output circuit. The data output circuit outputs data in synchronization with the delay-locked system clock. As a result, the data can be correctly output to the external circuit in synchronization with the system clock.
In an actual operation, the delay-locked system clock is transferred to the output buffer at a time point earlier by one period than a time point when the data must be outputted, and the output buffer outputs data in synchronization with the received delay locked system clock. Therefore, the data is outputted faster than the delay of the system clock caused by the internal circuit of the semiconductor memory device. In this way, it seems that the data may be correctly outputted in synchronization with the rising and falling edges of the system clock input to the semiconductor memory device. The DLL circuit is a circuit to seek how fast the data must be outputted in order to compensate for the internal delay of the system clock of the semiconductor memory device.
As a frequency of the system clock inputted in the semiconductor memory device is gradually increasing, an operating margin processed in order to output a data is gradually reducing. Accordingly, a duty ratio of the delay locked clock as a reference clock in order to output a data must keep up accurately 50% in order to maximize the operating margin outputting a data synchronized with a rising edge and a falling edge of the system clock. A recent DLL circuit includes a duty-correction circuit for correcting a duty ratio of the delay locked clock to 50%.
A most common method adjusting the duty ratio of the delay locked clock is performing a delay locked operation based on the rising edge of the system clock. At the same time, the delay locked operation based on the falling edge of the system clock is performed to generates a waveform including a transition which corresponds to a ½ location of a point of transition time of each delay locked clock. The DLL circuit includes two loop circuits in order to perform the delay locked operation based on the rising edge and the falling edge of the system clock. That is, because the DLL circuit includes two delay lines, the DLL circuit requires circuit blocks for duty-correction more than two times. In that case, there is a problem that a size of circuit and current consumption may be increased. Therefore, it is necessary to adjust the duty ratio of the delay locked clock to 50% for maximizing efficiency of the operating margin for outputting a data without requiring an extra circuit block.